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SCIn ISOSYNCHRONOUS MODE TIMINGS - INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode
(1) (2) (3)
Data Valid
Data Valid
SCICLK
SCITX
SCIRX
t
c(SCC)
t
w(SCCL)
t
w(SCCH)
t
d(SCCHĆTXV)
t
v(TX)
t
su(RXĆSCCL)
t
v(SCCLĆRX)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
(see Figure 17 )
(BAUD + 1) (BAUD + 1)
IS EVEN OR BAUD = 0 IS ODD AND BAUD ≠ 0
UNIT
MIN MAX MIN MAX
Cycle time,
t
c(SCC)
2t
c(ICLK)
2
24
t
c(ICLK)
3t
c(ICLK)
(2
24
– 1) t
c(ICLK)
ns
SCInCLK
Pulse duration,
t
w(SCCL)
0.5t
c(SCC)
– t
f
0.5t
c(SCC)
+ 5 0.5t
c(SCC)
+ 0.5t
c(ICLK)
– t
f
0.5t
c(SCC)
+ 0.5t
c(ICLK)
ns
SCInCLK low
Pulse duration,
t
w(SCCH)
0.5t
c(SCC)
– t
r
0.5t
c(SCC)
+ 5 0.5t
c(SCC)
– 0.5t
c(ICLK)
– t
r
0.5t
c(SCC)
– 0.5t
c(ICLK)
ns
SCInCLK high
Delay time,
t
d(SCCH-TXV)
SCInCLK high to 10 10 ns
SCInTX valid
Valid time,
SCInTX data
t
v(TX)
t
c(SCC)
– 10 t
c(SCC)
– 10 ns
after SCInCLK
low
Setup time,
t
su(RX-SCCL)
SCInRX before t
c(ICLK)
+ t
f
+ 20 t
c(ICLK)
+ t
f
+ 20 ns
SCInCLK low
Valid time,
SCInRX data
t
v(SCCL-RX)
–t
c(ICLK)
+ t
f
+ 20 –t
c(ICLK)
+ t
f
+ 20 ns
after SCInCLK
low
(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(2) t
c(ICLK)
= interface clock cycle time = 1/f
(ICLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
46
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