Datasheet

www.ti.com
SPIn SLAVE MODE TIMING PARAMETERS
SPIn Slave Mode External Timing Parameters
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1) (2) (3) (4)
(see Figure 15 )
NO. MIN MAX UNI
T
1 t
c(SPC)S
Cycle time, SPInCLK
(5)
100 256t
c(ICLK)
t
w(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0) 0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
2
(6)
t
w(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1) 0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
t
w(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0) 0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
3
(6)
t
w(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1) 0.5t
c(SPC)S
– 0.25t
c(ICLK)
0.5t
c(SPC)S
+ 0.25t
c(ICLK)
Delay time, SPInCLK high to SPInSOMI valid
t
d(SPCH-SOMI)S
6 + t
r
(clock polarity = 0)
4
(6)
Delay time, SPInCLK low to SPInSOMI valid
t
d(SPCL-SOMI)S
6 + t
f
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
t
v(SPCH-SOMI)S
t
c(SPC)S
– 6 – t
r
ns
(clock polarity = 0)
5
(6)
Valid time, SPInSOMI data valid after SPInCLK low
t
v(SPCL-SOMI)S
t
c(SPC)S
– 6 – t
f
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK low
t
su(SIMO-SPCL)S
6
(clock polarity = 0)
6
(6)
Setup time, SPInSIMO before SPInCLK high
t
su(SIMO-SPCH)S
6
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low
t
v(SPCL-SIMO)S
6
(clock polarity = 0)
7
(6)
Valid time, SPInSIMO data valid after SPInCLK high
t
v(SPCH-SIMO)S
6
(clock polarity = 1)
(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) If the SPI is in slave mode, the following must be true: t
c(SPC)S
≥ (PS + 1) t
c(ICLK)
, where PS = prescale value set in SPInCTL1[12:5].
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) t
c(ICLK)
= interface clock cycle time = 1/f
(ICLK)
(5) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)S
≥ (PS +1)t
c(ICLK)
≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t
c(SPC)S
= 2t
c(ICLK)
≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
43
Submit Documentation Feedback