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SPIn Master Mode External Timing Parameters
Data Valid
SPInSOMI
SPInSIMO
SPInCLK
(clock polarity = 1)
SPInCLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
2
3
4
5
6
7
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)
(1) (2) (3)
(see Figure 14 )
NO. MIN MAX UNIT
1 t
c(SPC)M
Cycle time, SPInCLK
(4)
100 256t
c(ICLK)
t
w(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0) 0.5t
c(SPC)M
– t
r
0.5t
c(SPC)M
+ 5
2
(5)
t
w(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1) 0.5t
c(SPC)M
– t
f
0.5t
c(SPC)M
+ 5
t
w(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0) 0.5t
c(SPC)M
– t
f
0.5t
c(SPC)M
+ 5
3
(5)
t
w(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1) 0.5t
c(SPC)M
– t
r
0.5t
c(SPC)M
+ 5
Valid time, SPInCLK high after SPInSIMO data valid
t
v(SIMO-SPCH)M
0.5t
c(SPC)M
– 10
(clock polarity = 0)
4
(5)
Valid time, SPInCLK low after SPInSIMO data valid
t
v(SIMO-SPCL)M
0.5t
c(SPC)M
– 10
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
– 5 – t
r
ns
(clock polarity = 0)
5
(5)
Valid time, SPInSIMO data valid after SPInCLK low
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
– 5 – t
f
(clock polarity = 1)
Setup time, SPInSOMI before SPInCLK high
t
su(SOMI-SPCH)M
6
(clock polarity = 0)
6
(5)
Setup time, SPInSOMI before SPInCLK low
t
su(SOMI-SPCL)M
6
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
t
v(SPCH-SOMI)M
4
(clock polarity = 0)
7
(5)
Valid time, SPInSOMI data valid after SPInCLK low
t
v(SPCL-SOMI)M
4
(clock polarity = 1)
(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2) t
c(ICLK)
= interface clock cycle time = 1/f
(ICLK)
(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(ICLK)
≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(ICLK)
≥ 100 ns.
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)
42
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