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Switching Characteristics over Recommended Operating Conditions for External Clocks
(1) (2) (3)
CLKOUT
t
w(COH)
t
w(COL)
ECLK
t
w(EOH)
t
w(EOL)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
(see Figure 7 and Figure 8 )
PARAMETER TEST CONDITIONS MIN MAX UNIT
SYSCLK or MCLK
(4)
0.5t
c(SYS)
– t
f
t
w(COL)
Pulse duration, CLKOUT low ICLK: X is even or 1
(5)
0.5t
c(ICLK)
– t
f
ns
ICLK: X is odd and not 1
(5)
0.5t
c(ICLK)
+ 0.5t
c(SYS)
– t
f
SYSCLK or MCLK
(4)
0.5t
c(SYS)
– t
r
t
w(COH)
Pulse duration, CLKOUT high ICLK: X is even or 1
(5)
0.5t
c(ICLK)
– t
r
ns
ICLK: X is odd and not 1
(5)
0.5t
c(ICLK)
– 0.5t
c(SYS)
– t
r
N is even and X is even or odd 0.5t
c(ECLK)
– t
f
t
w(EOL)
Pulse duration, ECLK low N is odd and X is even 0.5t
c(ECLK)
– t
f
ns
N is odd and X is odd and not 1 0.5t
c(ECLK)
+ 0.5t
c(SYS)
– t
f
N is even and X is even or odd 0.5t
c(ECLK)
– t
r
t
w(EOH)
Pulse duration, ECLK high N is odd and X is even 0.5t
c(ECLK)
– t
r
ns
N is odd and X is odd and not 1 0.5t
c(ECLK)
– 0.5t
c(SYS)
– t
r
(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
(2) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
(4) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
(5) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
Figure 7. CLKOUT Timing Diagram
Figure 8. ECLK Timing Diagram
36
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