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ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
Switching Characteristics over Recommended Operating Conditions for Clocks
(1) (2) (3)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
MIN TYP MAX UNIT
f
(OSC)
Input clock frequency 4 10 MHz
t
c(OSC)
Cycle time, OSCIN 100 ns
t
w(OSCIL)
Pulse duration, OSCIN low 15 ns
t
w(OSCIH)
Pulse duration, OSCIN high 15 ns
f
(OSCRST)
OSC FAIL frequency
(1)
53 kHz
(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
PARAMETER TEST CONDITIONS
(4)
MIN MAX UNIT
Pipeline mode enabled 60
(6)
MHz
f
(SYS)
System clock frequency
(5)
Pipeline mode disabled 24 MHz
f
(CONFIG)
System clock frequency - flash config mode 24 MHz
Pipeline mode enabled 30 MHz
f
(ICLK)
Interface clock frequency
Pipeline mode disabled 24 MHz
Pipeline mode enabled 30 MHz
f
(ECLK)
External clock output frequency for ECP module
Pipeline mode disabled 24 MHz
Pipeline mode enabled 16.7 ns
t
c(SYS)
Cycle time, system clock
Pipeline mode disabled 41.6 ns
t
c(CONFIG)
Cycle time, system clock - flash config mode 41.6 ns
Pipeline mode enabled 33.3 ns
t
c(ICLK)
Cycle time, interface clock
Pipeline mode disabled 41.6 ns
Pipeline mode enabled 33.3 ns
t
c(ECLK)
Cycle time, ECP module external clock output
Pipeline mode disabled 41.6 ns
(1) f
(SYS)
= M × f
(OSC)
/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f
(SYS)
= f
(OSC)
/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f
(ICLK)
= f
(SYS)
/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2) f
(ECLK)
= f
(ICLK)
/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) Only ZPLL mode is available. FM mode must not be turned on.
(4) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(5) Flash Vread must be set to 5 V to achieve maximum system clock frequency.
(6) Operating V
CC
range for this system clock frequency is 1.81 to 2.05 V.
35
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