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interrupt priority (IEM to CIM)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
Interrupt requests originating from the B1M peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.) are
assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register
mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS
module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order in
the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 6 .
Table 6. Interrupt Priority (IEM and CIM)
DEFAULT CIM INTERRUPT
MODULES INTERRUPT SOURCES IEM CHANNEL
LEVEL/CHANNEL
SPI1 SPI1 end-transfer/overrun 0 0
RTI COMP2 interrupt 1 1
RTI COMP1 interrupt 2 2
RTI TAP interrupt 3 3
SPI2 SPI2 end-transfer/overrun 4 4
GIO GIO interrupt A 5 5
Reserved 6 6
HET HET interrupt 1 7 7
I2C1 I2C1 interrupt 8 8
SCI1/SCI2 SCI1 or SCI2 error interrupt 9 9
SCI1 SCI1 receive interrupt 10 10
Reserved 11 11
I2C2 I2C2 interrupt 12 12
HECC1 HECC1 interrupt A 13 13
SCC SCC interrupt A 14 14
Reserved 15 15
MibADC MibADC end event conversion 16 16
SCI2 SCI2 receive interrupt 17 17
DMA DMA interrupt 0 18 18
I2C3 I2C3 interrupt 19 19
SCI1 SCI1 transmit interrupt 20 20
System SW interrupt (SSI) 21 21
Reserved 22 22
HET HET interrupt 2 23 23
HECC1 HECC1 interrupt B 24 24
SCC SCC interrupt B 25 25
SCI2 SCI2 transmit interrupt 26 26
MibADC MibADC end Group 1 conversion 27 27
DMA DMA Interrupt 1 28 28
GIO GIO interrupt B 29 29
MibADC MibADC end Group 2 conversion 30 30
SCI3 SCI3 error interrupt 31 31
21
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