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direct-memory access (DMA)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA
controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in parallel
with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the B1M device, the DMA controller
configuration is 32 control packets and 16 channels.
For the B1M DMA request hardwired configuration, see Table 5 .
Table 5. DMA Request Lines Connections
(1)
MODULES DMA REQUEST INTERRUPT SOURCES DMA CHANNEL
EBM Expansion Bus DMA request EBDMAREQ[0] DMAREQ[0]
SPI1/I2C4 SPI1 end-receive/I2C4 read SPI1DMA0/I2C4DMA0 DMAREQ[1]
SPI1/I2C4 SPI1 end-transmit/I2C4 write SPI1DMA1/I2C4DMA1 DMAREQ[2]
MibADC/I2C1 ADC EV/I2C1 read MibADCDMA0/I2C1DMA0 DMAREQ[3]
MibADC/SCI1/I2C5 ADC G1/SCI1 end-receive/I2C5 read MibADCDMA1/SCI1DMA0/I2C5DMA0 DMAREQ[4]
MibADC/SCI1/I2C5 ADC G2/SCI1 end-transmit/I2C5 write MibADCDMA2/SCI1DMA1/I2C5DMA1 DMAREQ[5]
I2C1 I2C1 write I2C1DMA1 DMAREQ[6]
SCI3/SPI2 SCI3 end-receive/SPI2 end-receive SCI3DMA0/SPI2DMA0 DMAREQ[7]
SCI3/SPI2 SCI3 end-transmit/SPI2 end-transmit SCI3DMA01SPI2DMA1 DMAREQ[8]
I2C2 I2C2 read end-receive I2C2DMA0 DMAREQ[9]
I2C2 I2C2 write end-transmit I2C2DMA1 DMAREQ[10]
I2C3 I2C3 read I2C3DMA0 DMAREQ[11]
I2C3 I2C3 write I2C3DMA1 DMAREQ[12]
Reserved DMAREQ[13]
SCI2 SCI2 end-receive SCI2DMA0 DMAREQ[14]
SCI2 SCI2 end-transmit SCI2DMA1 DMAREQ[15]
(1) For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a
given application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
• Non-request mode (used when transferring from memory to memory)
• Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
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