Datasheet

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TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
TERMINAL INTERNAL
CURRENT
TYPE
(1) (2)
PULLUP/ DESCRIPTION
OUTPUT
NAME NO.
PULLDOWN
(3)
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SDA 29 I2C3 serial data pin or GIO pin
5-V tolerant 4 mA
I2C3SCL 28 I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
I2C4SDA 41 I2C4 serial data pin or GIO pin
5-V tolerant 4 mA
I2C4SCL 40 I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
I2C5SDA 38 I2C5 serial data pin or GIO pin
5-V tolerant 4 mA
I2C5SCL 37 I2C5 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN 33 1.8 V Crystal connection pin or external clock input
OSCOUT 32 2 mA External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed
and the oscillator becomes the system clock. If not in
PLLDIS 97 3.3 V IPD (20 µA) bypass mode, TI recommends that this pin be
connected to ground or pulled down to ground by an
external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1 clock. SCI1CLK can be programmed as a GIO
SCI1CLK 48 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI1 data receive. SCI1RX can be programmed as a
SCI1RX 46 5-V tolerant 4 mA
GIO pin.
SCI1 data transmit. SCI1TX can be programmed as a
SCI1TX 45 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2 clock. SCI2CLK can be programmed as a GIO
SCI2CLK 51 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI2 data receive. SCI2RX can be programmed as a
SCI2RX 50 5-V tolerant 4 mA
GIO pin.
SCI2 data transmit. SCI2TX can be programmed as a
SCI2TX 49 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
SCI3 clock. SCI3CLK can be programmed as a GIO
SCI3CLK 24 3.3 V 2 mA -z IPD (20 µA)
pin.
SCI3 data receive. SCI3RX can be programmed as a
SCI3RX 22 5-V tolerant 4 mA
GIO pin.
SCI3 data transmit. SCI3TX can be programmed as a
SCI3TX 21 3.3 V 2 mA -z IPU (20 µA)
GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a
CLKOUT 81 3.3 V 8 mA
GIO pin or the output of SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External V
CC
PORRST 118 3.3 V IPD (20 µA)
monitor circuitry must assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a
reset, and an external system reset can assert a
device reset.
On this pin, the output buffer is implemented as an
RST 121 3.3 V 4 mA IPU (20 µA)
open drain (drives low only).
To ensure an external reset is not arbitrarily generated,
TI recommends that an external pullup resistor be
connected to this pin.
11
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