Serial RapidIO (SRIO) User's Guide

www.ti.com
Port0
8x276 TX
8x276RX
8x276RX
8x276 TX
Port1
8x276 TX
8x276RX
Port2
8x276RX
8x276 TX
Port3
Physical
layer
buffers
SERDES0 SERDES1 SERDES2 SERDES3
SERDES
differential
signals
4xmode
datapath
TXbuffering
32x276B
8buffersper1Xport-allpriorities
32buffersper4Xport-8perpriority
Transaction
mapping
layer
buffers
Logical
Load/Store
units(LSUs)
TXdirectI/O
Maintenance
Messaging
TXU
RXdirectI/O
(MAU)
Memory
accessunit
RXU
Messaging
buffer
4.5KB TX
shared
buffer
shared
4.5KBRX
handle
Queue
DMA bus
UDI
SRIO Functional Description
Figure 8. SRIO Component Block Diagram
SPRUE13A – September 2006 Serial RapidIO (SRIO) 27
Submit Documentation Feedback