Serial RapidIO (SRIO) User's Guide

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5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)
SRIO Registers
The port IP discovery timer for 4x mode register (SP_IP_DISCOVERY_TIMER) is shown in Figure 154
and described in Table 176 .
Figure 154. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address
Offset 12000h
31 28 27 24 23 20 19 16
DISCOVERY_TIMER Reserved PW_TIMER Reserved
R/W-9h R-0h R/W-8h R-0h
15 0
Reserved
R-0000h
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Table 176. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) Field
Descriptions
Bit Field Value Description
31–28 DISCOVERY_TIMER Discovery timer for 4x mode. The discovery timer allows time for the link partner
to enter its DISCOVERY state and if the link partner is supporting 4x mode, for
all 4 lanes to be aligned.
0000b Reserved
0001b 0.84 ms
0010b 0.84 ms x 2 = 1.68 ms
... ...
1001b 0.84 ms x 9= 7.56 ms (default)
... ...
1111b 0.84 ms x 15= 12.6 ms
27–24 Reserved 0000b These read-only bits return 0s when read.
23–20 PW_TIMER Port-write timer. The timer defines a period to repeat sending an error reporting
port-write request for software assistance. The timer is stopped by software
writing to the error detect registers.
0000b Disabled. Port-write is sent once only.
0001b 107 ms–214 ms
0010b 214 ms–321 ms
0100b 428 ms–535 ms
1000b 856 ms–963 ms (default)
Other Reserved
19–0 Reserved 0000h These read-only bits return 0s when read.
Serial RapidIO (SRIO)230 SPRUE13A – September 2006
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