Serial RapidIO (SRIO) User's Guide

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SerialRapidIO1xDeviceto1xDeviceInterfaceDiagram
SerialRapidIO4xDeviceto4xDeviceInterfaceDiagram
1xDevice
TD[0]
TD[0]
RD[0]
RD[0] TD[0]
TD[0]
1xDevice
RD[0]
RD[0]
RD[0-3]
RD[0-3]
4xDevice
TD[0-3]
RD[0-3]
RD[0-3]
TD[0-3]
4xDevice
TD[0-3]
TD[0-3]
1.2 RapidIO Feature Support in SRIO
Overview
Figure 3. Serial RapidIO Device to Device Interface Diagrams
Features Supported in SRIO Peripheral:
• RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
• Physical Layer 1x/4x LP-Serial Specification V1.2 compliance
• 4x Serial RapidIO with auto-negotiation to 1x port, optional operation for four 1x ports
• Integrated clock recovery with TI SERDES
• Hardware error handling including Cyclic Redundancy Code (CRC)
• Differential CML signaling supporting AC coupling
• Support for 1.25, 2.5, and 3.125 Gbps rates
• Power-down option for unused ports
• Read, write, write with response, streaming write, outgoing Atomic, and maintenance operations
• Generates interrupts to the CPU (Doorbell packets and internal scheduling)
• Support for 8-bit and 16-bit device ID
• Support for receiving 34-bit addresses
• Support for generating 34-bit, 50-bit, and 66-bit addresses
• Support for the following data sizes: byte, half-word, word, double-word
• Big endian data transfers
• Direct I/O transfers
• Message passing transfers
• Data payloads of up to 256 bytes
• Single messages consisting of up to 16 packets
• Elastic storage FIFOs for clock domain handoff
• Short run and long run compliance
• Support for Error Management Extensions
• Support for Congestion Control Extensions
• Support for one multi-cast ID
SPRUE13A – September 2006 Serial RapidIO (SRIO) 19
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