Serial RapidIO (SRIO) User's Guide

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5.51 Flow Control Table Entry Register n (FLOW_CNTL n)
SRIO Registers
There are sixteen of these registers (see Table 121 ). FLOW_CNTL n is shown in Figure 114 and described
in Table 122 . For additional programming information, see Section 2.3.8 .
Table 121. FLOW_CNTL n Registers
Register Address Offset
FLOW_CNTL0 0900h
FLOW_CNTL1 0904h
FLOW_CNTL2 0908h
FLOW_CNTL3 090Ch
FLOW_CNTL4 0910h
FLOW_CNTL5 0914h
FLOW_CNTL6 0918h
FLOW_CNTL7 091Ch
FLOW_CNTL8 0920h
FLOW_CNTL9 0924h
FLOW_CNTL10 0928h
FLOW_CNTL11 092Ch
FLOW_CNTL12 0930h
FLOW_CNTL13 0934h
FLOW_CNTL14 0938h
FLOW_CNTL15 093Ch
Figure 114. Flow Control Table Entry Register n (FLOW_CNTL n)
31 18 17 16
Reserved TT
R-0 R/W-01
15 0
FLOW_CNTL_ID
R/W-0000h
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Table 122. Flow Control Table Entry Register n (FLOW_CNTL n) Field Descriptions
Bit Field Value Description
31–18 Reserved 0 These read-only bits return 0s when read.
17–16 TT Transfer type for flow n
00b 8-bit destination IDs
01b 16-bit destination IDs
1xb Reserved
15–0 FLOW_CNTL_ID 0000h–FFFFh Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b),
the 8 MSBs of this field are don't care bits.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 181
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