Serial RapidIO (SRIO) User's Guide

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5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
SRIO Registers
This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer
descriptor queues. TX_CPPI_ICCR is shown in Figure 82 and described in Table 72 .
Figure 82. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Table 72. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions
Bit Field Value Description
31–16 Reserved 0 These read-only bits return 0 when read.
15–0 ICC x TX CPPI interrupt clear
(x = 15 to 0)
0 No effect
1 Clear bit x of TX_CPPI_ICSR.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 137
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