Serial RapidIO (SRIO) User's Guide

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5.3 Peripheral Control Register (PCR)
SRIO Registers
The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer
of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior
during emulation halts. PCR is shown in Figure 64 and described in Table 42 . For additional programming
information, see Section 2.3.11 .
Figure 64. Peripheral Control Register (PCR) - Address Offset 0004h
31 16
Reserved
R-0
15 3 2 1 0
Reserved PEREN SOFT FREE
R-0 R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Table 42. Peripheral Control Register (PCR) Field Descriptions
Bit Field Value Description
31–3 Reserved 0 These read-only bits return 0s when read.
2 PEREN Peripheral flow control enable. Controls the flow of data in the logical layer of the peripheral. As an
initiator, it will prevent TX transaction generation; as a target, it will disable incoming requests. This
should be the last enable bit to toggle when bringing the device out of reset to begin normal
operation.
0 Data flow control is disabled.
1 Data flow control is enabled.
1 SOFT Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation
halts.
0 Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO
peripheral.)
1 Soft stop
0 FREE Free run
0 The SOFT bit takes effect.
1 Free run. Peripheral ignores the emulation suspend signal and functions normally.
Serial RapidIO (SRIO)112 SPRUE13A – September 2006
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