Network Card User Manual

EMAC Port Registers

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5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)

The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 88 and

described in Table 82.

Figure 88. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)

31 16

TXnHDP

R/W-x

15 0

TXnHDP

R/W-x

LEGEND: R/W = Read/Write; -n = value after reset

Table 82. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions

Bit Field Value Description

31-0 TXnHDP Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor address

to a head pointer location initiates transmit DMA operations in the queue for the selected channel.

Writing to these locations when they are nonzero is an error (except at reset). Host software must

initialize these locations to zero on reset.

144

C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010

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