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EMAC Port Registers

5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)

The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 65 and described in Table 59.

Figure 65. Receive Unicast Clear Register (RXUNICASTCLEAR)

31 16

Reserved

R-0

15 8 7 6 5 4 3 2 1 0

Reserved RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN RXCH0EN

R-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset

Table 59. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Reserved

7 RXCH7EN Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

6 RXCH6EN Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

5 RXCH5EN Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

4 RXCH4EN Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

3 RXCH3EN Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

2 RXCH2EN Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

1 RXCH1EN Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

0 RXCH0EN Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

119

SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO

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