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EMAC Port Registers

5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 59 and described

in Table 53.

Figure 59. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

31 16

Reserved

R-0

15 2 1 0

HOST STAT

Reserved

PEND PEND

R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 53. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTPEND Host pending interrupt (HOSTPEND); raw interrupt read (before mask)

0 STATPEND Statistics pending interrupt (STATPEND); raw interrupt read (before mask)

111

SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO

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