Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external memory interface read timing
switching characteristics over recommended operating conditions for an external memory
interface read at 40 MHz [H = 0.5t
c(CO)
] (see Figure 46)
PARAMETER MIN MAX UNIT
t
d(COL-CNTL)
Delay time, CLKOUT low to control valid
4 ns
t
d(COL-CNTH)
Delay time, CLKOUT low to control inactive
5 ns
t
d(COL-A)RD
Delay time, CLKOUT low to address valid
8 ns
t
d(COH-RDL)
Delay time, CLKOUT high to RD strobe active
5 ns
t
d(COL-RDH)
Delay time, CLKOUT low to RD strobe inactive high
−8 1 ns
t
d(COL-SL)
Delay time, CLKOUT low to STRB strobe active low
5 ns
t
d(COL-SH)
Delay time, CLKOUT low to STRB strobe inactive high
6 ns
t
d(WRN)
Delay time, W/R going low to R/W rising
5 ns
t
h(A)COL
Hold time, address valid after CLKOUT low
2 ns
t
su(A)RD
Setup time, address valid before RD strobe active low
H − 7 ns
t
h(A)RD
Hold time, address valid after RD strobe inactive high
0 ns
timing requirements [H = 0.5t
c(CO)
] (see Figure 46)
MIN MAX UNIT
t
a(A)
Access time, read data from address valid
2H −10 ns
t
a(RD)
Access time, read data from RD low
H − 7 ns
t
su(D)RD
Setup time, read data before RD strobe inactive high
8 ns
t
h(D)RD
Hold time, read data after RD strobe inactive high
0 ns
t
h(AIV-D)
Hold time, read data after address invalid
0 ns