Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPI slave mode timing parameters
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)
†‡
(see Figure 44)
NO. MIN MAX UNIT
12 t
c(SPC)S
Cycle time, SPICLK 4t
c(CO)
‡
ns
13
§
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0) 0.5t
c(SPC)S
−10 0.5t
c(SPC)S
13
§
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1) 0.5t
c(SPC)S
−10 0.5t
c(SPC)S
ns
14
§
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0) 0.5t
c(SPC)S
−10 0.5t
c(SPC)S
14
§
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1) 0.5t
c(SPC)S
−10 0.5t
c(SPC)S
ns
15
§
t
d(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375t
c(SPC)S
−10
ns
15
§
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375t
c(SPC)S
−10
ns
16
§
t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75t
c(SPC)S
16
§
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75t
c(SPC)S
ns
19
§
t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0
19
§
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0
ns
20
§
t
v(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5t
c(SPC)S
ns
20
§
t
v(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5t
c(SPC)S
ns
†
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
‡
t
c
= system clock cycle time = 1/CLKOUT = t
c(CO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).