Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
interrupt timing
INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
switching characteristics over recommended operating conditions (see Figure 39)
PARAMETER MIN MAX UNIT
t
Dela
y
time, PDPINTA low to PWM
if bit 6 of SCSR2 = 0 (6 + 1)t
c(CO)
+ 12
†
ns
t
d(PDP-PWM)HZ
Delay time
,
PDPINTA low to PWM
high-impedance state
if bit 6 of SCSR2 = 1
(12+ 1)t
c(CO)
+ 12
†
ns
t
d(INT)
Delay time, INT low/high to interrupt-vector
fetch
10t
c(CO)
+ t
W
(INT) ns
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 39)
MIN MAX UNIT
t
†
Pulse duration INT input low/high
if bit 6 of SCSR2 = 0
6t
c(CO)
ns
t
w(INT)
†
Pulse duration, INT input low/high
if bit 6 of SCSR2 = 1
12t
c(CO)
ns
t
†
Pulse duration PDPINTx input low
if bit 6 of SCSR2 = 0
6t
c(CO)
ns
t
w(PDP)
†
Pulse duration, PDPINTx input low
if bit 6 of SCSR2 = 1
12t
c(CO)
ns
†
This is different from 240x devices.
PWM
†
PDPINTx
CLKOUT
t
w(PDP)
t
d(PDP-PWM)HZ
XINT1, XINT2
t
w(INT)
Interrupt Vector
t
d(INT)
†
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken
high depends on the state of the FCOMPOE bit.
A0−A15
Figure 39. External Interrupts Timing