Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TIMING EVENT MANAGER INTERFACE
PWM timing
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t
c(CO)
] (see Figure 36)
PARAMETER MIN MAX UNIT
t
w(PWM)
†
Pulse duration, PWMx output high/low
2H+5 ns
t
d(PWM)CO
Delay time, CLKOUT low to PWMx output switching
15 ns
†
PWM outputs may be 100%, 0%, or increments of t
c(CO)
with respect to the PWM period.
timing requirements
‡
[H = 0.5t
c(CO)
] (see Figure 37)
MIN MAX UNIT
t
w(TMRDIR)
Pulse duration, TMRDIR low/high
4H+5 ns
t
w(TMRCLK)
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
40 60 %
t
wh(TMRCLK)
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
40 60 %
t
c(TMRCLK)
Cycle time, TMRCLK
4  t
c(CO)
ns
‡
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
t
w(PWM)
t
d(PWM)CO
PWMx
CLKOUT
Figure 36. PWM Output Timing
CLKOUT
t
w(TMRDIR)
TMRDIR
†
†
Parameter TMRDIR is equal to the pin TDIRx.
Figure 37. TMRDIR Timing