Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
LPM2 wakeup timing
switching characteristics over recommended operating conditions (see Figure 34)
PARAMETER MIN MAX UNIT
t
Dela
y
time, PDPINTA low to PWM
if bit 6 of SCSR2 = 0 (6 + 1)t
c(CO)
+ 12
†
ns
t
d(PDP-PWM)HZ
Delay time
,
PDPINTA low to PWM
high-impedance state
if bit 6 of SCSR2 = 1
(12+ 1)t
c(CO)
+ 12
†
ns
t
d(INT)
Delay time, INT low/high to interrupt-vector
fetch
10t
c(CO)
+ t
w
(PDP−WAKE) ns
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 34)
MIN MAX UNIT
t
‡
Pulse duration PDPINTA input low
if bit 6 of SCSR2 = 0 6t
c(CO)
ns
t
w(PDP−WAKE)
‡
Pulse duration, PDPINTA input low
if bit 6 of SCSR2 = 1
12t
c(CO)
ns
t
p
PLL lock-up time 4096t
c(CI)
cycles
‡
This is different from 240x devices.
PWM
PDPINTx
CLKOUT
‡
t
w(PDP−WAKE)
t
d(PDP-PWM)HZ
CPU Status
Interrupt Vector
§
or
Next Instruction
¶
t
d(INT)
XTAL1
Oscillator Disabled
CLKIN
t
p
t
OSC
†
CPU IDLE State (LPM2)
†
t
OSC
is the oscillator start-up time.
‡
CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example).
§
PDPINTx interrupt vector, if PDPINTx interrupt is enabled.
¶
If PDPINTx interrupt is disabled.
Figure 34. LPM2 Wakeup Using PDPINTx