Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RS timing (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5t
c(CO)
]
(see Figure 30)
PARAMETER MIN MAX UNIT
t
w(RSL1)
Pulse duration, RS low
†
128t
c(CI)
ns
t
d(EX)
Delay time, reset vector executed after PLL lock time
36H ns
t
p
PLL lock time (input cycles)
4096t
c(CI)
ns
†
The parameter t
w(RSL1)
refers to the time RS is an output.
XTAL1
†
Address/
Data/
Control
CLKOUT
RS
t
w(RSL1)
t
p
t
d(EX)
CLKIN
BOOT_EN
/XF
BOOT_EN
I/Os
XF
Code-Dependent
Address/Data/Control Valid
Hi-Z
†
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
Figure 30. Watchdog Initiated Reset