Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external reference crystal/clock with PLL circuit enabled
timing parameters with the PLL circuit enabled
PARAMETER MIN MAX UNIT
Resonator 4 13
f
x
Input clock frequency
†
Crystal 4 20
MHz
f
x
Input clock frequency
CLKIN 4 20
MHz
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 27)
PARAMETER PLL MODE MIN TYP MAX UNIT
t
c(CO)
Cycle time, CLKOUT
×4 mode
†
25 ns
t
f(CO)
Fall time, CLKOUT 4 ns
t
r(CO)
Rise time, CLKOUT 4 ns
t
w(COL)
Pulse duration, CLKOUT low H −3 H H+3 ns
t
w(COH)
Pulse duration, CLKOUT high H −3 H H+3 ns
t
t
Transition time, PLL synchronized after RS pin high
4096t
c(Cl)
ns
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
timing requirements (see Figure 27)
MIN MAX UNIT
t
c(Cl)
Cycle time, XTAL1/CLKIN
250 ns
t
f(Cl)
Fall time, XTAL1/CLKIN 5 ns
t
r(Cl)
Rise time, XTAL1/CLKIN 5 ns
t
w(CIL)
Pulse duration, XTAL1/CLKIN low as a percentage of t
c(Cl)
40 60 %
t
w(CIH)
Pulse duration, XTAL1/CLKIN high as a percentage of t
c(Cl)
40 60 %
XTAL1/CLKIN
t
c(CI)
t
w(CIL)
t
w(CIH)
t
f(Cl)
t
r(Cl)
t
c(CO)
t
w(COH)
t
w(COL)
t
r(CO)
t
f(CO)
CLKOUT
Figure 27. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode