Datasheet

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
serial peripheral interface (SPI) module (continued)
Figure 15 is a block diagram of the SPI in slave mode.
S
S
Clock
Polarity
Talk
Internal
Clock
456
012
SPI Bit Rate
State Control
SPIRXBUF
Buffer Register
16
Clock
Phase
1230
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 −0
SPIBRR.6 −0
SPICCR.6 SPICTL.3
SPIRXBUF.15−0
SPIDAT.15−0
SPICTL.1
M
S
M
Master/Slave
SPI INT FLAG
SPICTL.0
SPI INT
ENA
SPISTS.7
SPIDAT
Data Register
SPISTS.6
M
S
SPICTL.2
SPI Char
External
Connections
SPISIMO
SPISOMI
SPISTE
†
SPICLK
SW2
S
M
M
S
SW3
To CPU
M
SW1
SPIPRI.6
SPI Priority
Level 1
INT
1
0
Level 5
INT
SPITXBUF.15−0
3
16
SPITXBUF
Buffer Register
NOTE A: The diagram is shown in the slave mode.
†
The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. See the following errata for restrictions
on using the SPISTE
pin:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata
(literature number SPRZ002)
TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185)
Figure 15. Four-Pin Serial Peripheral Interface Module Block Diagram