Datasheet

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device reset and interrupts (continued)
CPU
IACK
Addr BusData Bus
PIVR & Logic
PIRQR#
PIACK#
IRQ GEN
Level 6
IRQ GEN
Level 5
IRQ GEN
Level 4
IRQ GEN
Level 3
IRQ GEN
Level 2
IRQ GEN
Level 1
ADCINT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
CAP3INT
CAP2INT
CAP1INT
T2OFINT
T2UFINT
T2CINT
T2PINT
T1OFINT
T1UFINT
T1CINT
T1PINT
CMP3INT
CMP2INT
CMP1INT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
ADCINT
PDPINTB
INT1
INT2
INT3
INT4
INT6
INT5
IMR
IFR
PIE
CAP6INT
CAP5INT
CAP4INT
T4OFINT
T4UFINT
T4CINT
T4PINT
CMP6INT
CMP5INT
CMP4INT
T3OFINT
T3UFINT
T3PINT
T3CINT
PDPINTA
Indicates change with respect to the TMS320F243/F241/C242 data sheets.
XINT1
XINT2
XINT1
XINT2
Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals.
Figure 9. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts