Datasheet

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
†‡
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK (CONTINUED)
XINT1/IOPA2 23 16 16
External user interrupt 1 or GPIO. Both XINT1 and XINT2
are edge-sensitive. The edge polarity is
programmable. (↑)
XINT2/ADCSOC/IOPD0 21 15 15 42
External user interrupt 2 and ADC start of conversion or
GPIO. External “start-of-conversion” input for ADC/GPIO.
Both XINT1 and XINT2 are edge-sensitive. The edge
polarity is programmable. (↑)
CLKOUT/IOPE0 73 51 51 1
Clock output or GPIO. This pin outputs either the CPU clock
(CLKOUT) or the watchdog clock (WDCLK). The selection
is made by the CLKSRC bit (bit 14) of the system control
and status register (SCSR). This pin can be used as a GPIO
if not used as a clock output pin. (↑)
PDPINTB 137 95 95
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVB) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTB
is a falling-edge-sensitive interrupt. (↑)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
XTAL1/CLKIN 123 87 87 24
PLL oscillator input pin. Crystal input to PLL/clock source
input to PLL. XTAL1/CLKIN is tied to one side of a reference
crystal.
XTAL2 124 88 88 25
Crystal output. PLL oscillator output pin. XTAL2 is tied to
one side of a reference crystal. This pin goes in the
high-impedance state when EMU1/OFF
is active low.
PLLV
CCA
12 10 10 39 PLL supply (3.3 V)
IOPF6 131 92 92 General-purpose I/O (↑)
BOOT
_
EN /
BOOT_EN 121 86 − 23
Boot ROM enable, GPO, XF. This pin will be sampled as
input (BOOT_EN
) to update SCSR2.3 (BOOT_EN bit)
durin
g
reset and then driven as an out
p
ut si
g
nal for XF. After
BOOT
_
EN /
XF
XF 121 86 86 23
during reset and then driven as an output signal for XF
.
After
reset, XF is driven high. ROM devices do not have boot
ROM, hence, no BOOT_EN modes. The BOOT_EN
pin
must be driven with a passive circuit only. (↑)
PLLF 11 9 9 38 PLL loop filter input 1
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (V
DD
, V
DDO
, V
CCA
, V
SS
, or V
SSO
) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)