Datasheet

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
†‡
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX/IOPC7
CANRX 70 49 − 63 CAN receive data or GPIO (LF2403A) (↑)
CANRX/IOPC7
IOPC7 70 49 49 63 GPIO only (2402A) (↑)
CANTX/IOPC6
CANTX 72 50 − 64 CAN transmit data or GPIO (LF2403A) (↑)
CANTX/IOPC6
IOPC6 72 50 50 64 GPIO only (2402A) (↑)
SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO (↑)
SCIRXD/IOPA1 26 18 18 44
SCI asynchronous serial port receive data or or
GPIO (↑)
SPICLK/IOPC4
SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) (↑)
SPICLK/IOPC4
IOPC4 35 24 24 47 GPIO only (2402A) (↑)
SPISIMO/IOPC2
SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) (↑)
SPISIMO/IOPC2
IOPC2 30 21 21 45 GPIO only (2402A) (↑)
SPISOMI/IOPC3
SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) (↑)
SPISOMI/IOPC3
IOPC3 32 22 22 46 GPIO only (2402A) (↑)
SPISTE/IOPC5
SPISTE 33 23 23 −
SPI slave transmit enable (optional) or GPIO (↑)
SPISTE/IOPC5
IOPC5 33 23 23 −
SPI slave transmit-enable (optional) or GPIO (↑)
EXTERNAL INTERRUPTS, CLOCK
RS 133 93 93 28
Device Reset (in) and Watchdog Reset (out).
Device reset. RS causes the device to terminate execution
and to set PC = 0. When RS
is brought to a high level,
execution begins at location 0x0000 of program memory.
This pin is driven low by the DSP when a watchdog reset
occurs. During watchdog reset, the RS
pin will be driven
low for the watchdog reset duration of 128 CLKIN cycles.
The output buffer of this pin is an open-drain with an
internal pullup (20 µA, typical). It is recommended that this
pin be driven by an open-drain device. (↑)
PDPINTA 7 6 6 36
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTA
is a falling-edge-sensitive interrupt. (↑)
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (V
DD
, V
DDO
, V
CCA
, V
SS
, or V
SSO
) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)