Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
125
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REG
KEY REGISTERS
077F0h
High Word of the 64 Bit KEY Register
KEY3
077F0h High Word of the 64-Bit KEY Register KEY3
077F1h
Third Word of the 64 Bit KEY Register
KEY2
077F1h Third Word of the 64-Bit KEY Register KEY2
077F2h
Second Word of the 64 Bit KEY Register
KEY1
077F2h Second Word of the 64-Bit KEY Register KEY1
077F3h
Low Word of the 64 Bit KEY Register
KEY0
077F3h Low Word of the 64-Bit KEY Register KEY0
PROGRAM MEMORY SPACE − FLASH REGISTERS
0xx00h
— — — — — — — —
PMPC
0xx00h
—
— — — PWR DWN KEY1 KEY0 EXEC
PMPC
0xx01h
— — — — — — WSVER EN
PRECND
Mode1
CTRL
†
0xx01h
PRECND
Mode0
ENG/R
Mode2
ENG/R
Mode1
ENG/R
Mode0
FCM3 FCM2 FCM1 FCM0
CTRL
†
0xx02h
WADDR
0xx02h WADDR
0xx03h
WDATA
0xx03h WDATA
0xx04h
— — — — — — — —
TCR
0xx04h
—
— — — — — — —
TCR
0xx05h
— — — — — — — —
ENAB
0xx05h
—
— — — — — — —
ENAB
— — — — — — — —
0xx06h
—
— — —
SECT 4
ENABLE
SECT 3
ENABLE
SECT 2
ENABLE
SECT 1
ENABLE
SECT
I/O MEMORY SPACE
0FF0Fh
— — — — — — — —
FCMR
0FF0Fh
—
— — — — — — —
FCMR
WAIT-STATE GENERATOR CONTROL REGISTER
0FFFFh
— — — — — BVIS.1 BVIS.0 ISWS.2
WSGR
0FFFFh
ISWS.1
ISWS.0 DSWS.2 DSWS.1 DSWS.0 PSWS.2 PSWS.1 PSWS.0
WSGR
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.
†
Register shown with bits set in register mode.