Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
109
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
10-bit analog-to-digital converter (ADC) (continued)
internal ADC module timing
†
(see Figure 52)
MIN MAX UNIT
t
C l ti ADC al d l k
33 3
t
c
(
AD
)
Cycle time, ADC prescaled clock 33.3 ns
Pulse duration total sample/hold and
t
w(SHC)
P
u
l
se
d
urat
i
on, tota
l
samp
l
e
/h
o
ld
an
d
i ti
‡
500
ns
t
w(SHC)
conversion time
‡
500
ns
t
d(SOC-SH)
Delay time, start of conversion to beginning of sample and hold 2t
c(CO)
ns
t
w(SH)
Pulse duration, sample and hold time 2t
c(AD)
§
32t
c(AD)
ns
t
w(C)
Pulse duration, total conversion time 10t
c(AD)
ns
t
d(EOC)
Delay time, end of conversion to data loaded into result register 2t
c(CO)
ns
t
d(ADCINT)
Delay time, ADC flag to ADC interrupt 2t
c(CO)
ns
†
The ADC timing diagram represents a typical conversion sequence. See the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference
Guide: System and Peripherals (literature number SPRU357) for more details.
‡
The total sample/hold and conversion time is determined by the summation of t
d(SOC-SH)
, t
w(SH)
, t
w(C)
, and t
d(EOC)
.
§
Can be varied by ACQ Prescaler bits in the ADCTRL1 register
03
2
451
t
w(C)
678
t
c(AD)
ADC Clock
Analog Input
Bit Converted
t
d(SOC−SH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to RESULTn
t
w(SHC)
t
d(EOC)
9
t
w(SH)
t
d(ADCINT)
ADC Interrupt
Figure 52. Analog-to-Digital Internal Module Timing