Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
104
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external memory interface ready-on-read timing (continued)
timing requirements for an external memory interface ready-on-read with one software wait state
and one external wait state (see Figure 49)
MIN MAX UNIT
t
h(RDY)COH
Hold time, READY after CLKOUT high
H − 2.5 ns
t
su(RDY)COH
Setup time, READY before CLKOUT high
H − 9.5 ns
t
d(COL-A)RD
Delay time, CLKOUT low to address valid
8 ns
PS, DS, IS
RD
READY
SW = 1 cycle EXW = 1 cycle Read Cycle
t
h(RDY)COH
t
su(RDY)COH
CLKOUT
R/W
W/R
D[0:15]
STRB
A[0:15]
t
d(COL-A)RD
Figure 49. Ready-on-Read Timings With One Software Wait (SW) State and
One External Wait (EXW) State