Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external memory interface ready-on-read timing
switching characteristics over recommended operating conditions for an external memory
interface ready-on-read (see Figure 48)
PARAMETER MIN MAX UNIT
t
d(COL-A)RD
Delay time, CLKOUT low to address valid
8 ns
timing requirements for an external memory interface ready-on-read (see Figure 48)
MIN MAX UNIT
t
h(RDY)COH
Hold time, READY after CLKOUT high
−3 ns
t
su(D)RD
Setup time, read data before RD strobe inactive high
8 ns
t
v(RDY)ARD
Valid time, READY after address valid on read
−2 ns
t
su(RDY)COH
Setup time, READY before CLKOUT high
22 ns
t
h(RDY)COH
CLKOUT
PS, DS, IS
RD
D[0:15]
STRB
A[0:15]
t
d(COL−A)RD
t
v(RDY)ARD
t
su(RDY)COH
READY
†
Wait Cycle
t
su(D)RD
†
The WSGR register must be programmed before the READY pin can be used. See the READY pin description for more details.
Figure 48. Ready-on-Read Timings