Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
114
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 19. LF240xA/LC240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REG
WD CONTROL REGISTERS
07020h
to
07022h
Illegal
07023h D7 D6 D5 D4 D3 D2 D1 D0 WDCNTR
07024h Illegal
07025h D7 D6 D5 D4 D3 D2 D1 D0 WDKEY
07026h
to
07028h
Illegal
07029h WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 WDCR
0702Ah
to
0703Fh
Illegal
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
07040h
SPI SW
RESET
CLOCK
POLARITY
— —
SPI
CHAR3
SPI
CHAR2
SPI
CHAR1
SPI
CHAR0
SPICCR
07041h — — —
OVERRUN
INT ENA
CLOCK
PHASE
MASTER/
SLAVE
TALK
SPI INT
ENA
SPICTL
07042h
RECEIVER
OVERRUN
FLAG
SPI INT
FLAG
TX BUF
FULL FLAG
— — — — — SPISTS
07043h Illegal
07044h —
SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
SPI BIT
RATE 0
SPIBRR
07045h Illegal
07046h
ERXB15 ERXB14 ERXB13 ERXB12 ERXB11 ERXB10 ERXB9 ERXB8
SPIRXEMU
07046h
ERXB7
ERXB6 ERXB5 ERXB4 ERXB3 ERXB2 ERXB1 ERXB0
SPIRXEMU
07047h
RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8
SPIRXBUF
07047h
RXB7
RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0
SPIRXBUF
07048h
TXB15 TXB14 TXB13 TXB12 TXB11 TXB10 TXB9 TXB8
SPITXBUF
07048h
TXB7
TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0
SPITXBUF
07049h
SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8
SPIDAT
07049h
SDAT7
SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0
SPIDAT
0704Ah
0704Ah
to
Ille
g
al
to
0704Eh
Illegal
0704Fh —
SPI
PRIORITY
SPI
SUSP SOFT
SPI
SUSP FREE
— — — — SPIPRI
Indicates change with respect to the F243/F241 C242 device register maps
Indicates change with respect to the F243/F241, C242 device register maps.