Datasheet

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external memory interface write timing
switching characteristics over recommended operating conditions for an external memory
interface write at 40 MHz [H = 0.5t
c(CO)
] (see Figure 47)
PARAMETER MIN MAX UNIT
t
d(COH-CNTL)
Delay time, CLKOUT high to control valid
4 ns
t
d(COH-CNTH)
Delay time, CLKOUT high to control inactive
5 ns
t
d(COH-A)W
Delay time, CLKOUT high to address valid
10 ns
t
d(COH-RWL)
Delay time, CLKOUT high to R/W low
6 ns
t
d(COH-RWH)
Delay time, CLKOUT high to R/W high
6 ns
t
d(COL-WL)
Delay time, CLKOUT low to WE strobe active low
6 ns
t
d(COL-WH)
Delay time, CLKOUT low to WE strobe inactive high
6 ns
t
en(D)COL
Enable time, data bus driven from CLKOUT low
−3 ns
t
d(COL-SL)
Delay time, CLKOUT low to STRB active low
6 ns
t
d(COL-SH)
Delay time, CLKOUT low to STRB inactive high
6 ns
t
d(WRN)
Delay time, R/W rising to W/R going low
5 ns
t
h(A)COLW
Hold time, address valid after CLKOUT low
−5 ns
t
su(A)W
Setup time, address valid before WE strobe active low
H−9 ns
t
su(D)W
Setup time, write data before WE strobe inactive high
2H−17 ns
t
h(D)W
Hold time, write data after WE strobe inactive high
2 ns
t
dis(W-D)
Disable time, data bus high impedance from WE high
5 ns