Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
terminal functions
Terminal Functions
†
TERMINAL
DESCRIPTION
NAME NO.
DESCRIPTION
RS 9
Device Reset (in) and Watchdog Reset (out).
Device reset. RS
causes the device to terminate execution and to set PC = 0. When RS is brought to
a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP
when a watchdog reset occurs. During watchdog reset, the RS
pin will be driven low for the watchdog
reset duration of 128 CLKIN cycles.
The output buffer of this pin is an open-drain with an internal pullup (20 µA, typical). It is recommended
that this pin be driven by an open-drain device. (↑)
PDPINTA/IOPA0 32
Power drive protection input. When this pin is pulled low by an external event, an interrupt is generated
and all PWM outputs go to high-impedance state. PDPINTA
will keep PWM outputs in high-impedance
state even when the DSP is not executing. (↑)
NOTES:
1) Upon reset, the PDPINTA function is active, in addition to the GPIO function. If the IOPA0 function
is desired, the PDPINTA
function must be disabled. (This can be done by writing to bit 0 of the
EVAIMRA register.) Otherwise, the PWM outputs could inadvertently be put into a high-impedance
state when the IOPA0 pin is driven low.
2) When PDPINTA
is used to “wake up” the DSP from LPM2, the pin should be held low for
(98304 CLKIN + 12 CLKOUT) cycles.
3) This pin must be held high when on-chip boot ROM is invoked.
PWM1/IOPA1 27 Compare/PWM output 1 or GPIO (↑)
PWM2/IOPA2 28 Compare/PWM output 2 or GPIO (↑)
PWM3/IOPA3 29 Compare/PWM output 3 or GPIO (↑)
PWM4/IOPA4 10 Compare/PWM output 4 or GPIO (↑)
PWM5/IOPA5 11 Compare/PWM output 5 or GPIO (↑)
PWM6/IOPA6 12 Compare/PWM output 6 or GPIO (↑)
T2PWM/XINT1/IOPB0 31
Upon reset, this pin comes up as XINT1/IOPB0 pin. To enable the XINT1 function, the appropriate bit
in the XINT1CR register must be set. No special configuration sequence is needed to use this pin as
a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a
general-purpose output. Configuration of this pin as T2PWM is achieved by writing a one to bit 8 of the
MCRA register. Note that the value of bit 8 in the MCRA register does not affect the XINT1 functionality
of this pin. The XINT1 function is enabled/disabled by the value written into the XINT1CR register and
is independent of the value written in bit 8 in the MCRA register. (↑)
XINT2/ADCSOC/CAP1/
IOPA7/CLKOUT
22
Upon reset, this pin can be configured as any one of the following: XINT2, ADCSOC, CAP1, or IOPA7.
To configure this pin for XINT2 function, the appropriate bit in the XINT2CR register must be set. To
configure this pin for ADCSOC function, the appropriate bit in the ADCTRL2 register must be set. To
configure this pin for CAP1 function, the appropriate bits in the CAPCONA register must be configured.
To summarize, the XINT2, ADCSOC, and CAP1 functions are enabled at the respective peripheral level.
No special configuration sequence is needed to use this pin as a GPIO. However, a write to the
PADATDIR register is necessary to configure this pin as a general-purpose output. This pin can also
function as the CPU clock output. This is achieved by writing a one to bit 7 of the MCRA register. When
CLKOUT is chosen, the internal logic for the XINT2, ADCSOC, and CAP1 sees the pin as a “1”. (↑)
†
Bold face type indicates function of the device pin after reset.
‡
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
§
TDI is MUXed with digital output, not digital I/O.
¶
Pin 26 is V
CCP
on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.)
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.