Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
ADDR
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
REG
ADDR
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
REG
WD CONTROL REGISTERS
07020h
to
07022h
Illegal
07023h D7 D6 D5 D4 D3 D2 D1 D0 WDCNTR
07024h Illegal
07025h D7 D6 D5 D4 D3 D2 D1 D0 WDKEY
07026h
to
07028h
Illegal
07029h WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 WDCR
0702Ah
to
0703Fh
Illegal
07040h
to
0704Fh
Reserved
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
07050h
STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOP BACK
ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
SCI
CHAR0
SCICCR
07051h —
RX ERR
INT ENA
SW RESET — TXWAKE SLEEP TXENA RXENA SCICTL1
07052h
BAUD15
(MSB)
BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD
07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1
BAUD0
(LSB)
SCILBAUD
07054h TXRDY TX EMPTY — — — —
RX/BK
INT ENA
TX
INT ENA
SCICTL2
07055h RX ERROR RXRDY BRKDT FE OE PE RXWAKE — SCIRXST
07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 SCIRXEMU
07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 SCIRXBUF
07058h Illegal
07059h TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 SCITXBUF
0705Ah
to
0705Eh
Illegal
0705Fh —
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
SOFT
SCI
FREE
— — — SCIPRI
07060h
to
0706Fh
Illegal
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.