Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EV
The Event Manager of the Lx2401A has reduced functionality when compared to that of the 240xA family.
Following are the important differences:
D There is no QEP unit.
D There is only one “Capture” input (CAP1).
D Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM).
D There is no provision to feed an external clock to the timers.
D There is no external direction control pin for the timers.
Due to these differences, some of the bits in the EV registers are not applicable in the Lx2401A and are shaded
gray. Refer to Table 16, Lx2401A DSP Peripheral Register Description, for more details.
ADC
The Lx2401A ADC has only five input channels as compared to eight or sixteen channels in the 240xA family.
Therefore, the 4-bit fields in the CHSELSEQn registers should be programmed with values from 0−4 only.
The Lx2401A ADC does not have dedicated V
REFHI
and V
REFLO
pins. Instead, the V
CCA
and V
SSA
pins provide
the necessary reference.
pins
The following pins, which are available in other 240xA devices, have been internally tied as indicated:
CAP2, CAP3 − low
TDIRA − low
TCLKINA − low
BIO
− high
DINR
The device ID contained in the DINR register is 0810h for LF2401A and 0910h for LC2401A.
XF pin
The XF pin has to be enabled by writing a 1 to Bit 0 of the SCSR4 register before it can be used.
migrating from LF2401A (Flash) device to LC2401A (ROM) device
When migrating from Flash to ROM device, be sure to review this section for a list of important differences that
should be considered. Customer applications should consider these differences in their design, prior to ROM
code submission. Due to the fact that the flash and ROM are different silicon, the following parameters may be
similar but not exactly identical. Refer to the respective datasheet sections for more detail:
D EMI/ESD behavior
D ADC performance
D Current consumption
D Device ID register values
D The last 64 words of ROM are reserved for TI internal testing. User code should not occupy these locations.
See the device memory map for details.