Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Flash parameters @40 MHz CLOCKOUT (LF2401A)
PARAMETER MIN TYP MAX UNIT
Clear/Programming time
†
Time/Word (16-bit) 30 µs
Clear/Programming time
†
Time/4K Sector 130 ms
Erase time
†
Time/4K Sector 350 ms
I
CCP
(V
CCP
pin current)
Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle
5 15 mA
†
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when V
DD
= 3.3 V and V
CCP
= 5 V, and any deviation from these values could affect the timing parameters. Aging and process
variance could also impact the timing parameters.
migrating from other 240xA devices to Lx2401A
This section outlines some of the issues to be considered while migrating a design from the 240xA family to the
Lx2401A. The Lx2401A shares the same CPU core (and hence, the same instruction set) as the 240xA.
Furthermore, the peripherals implemented on the Lx2401A are a subset of those found in the 240xA family.
However, some features of a particular peripheral may not be present on the 2401A. This must be taken into
consideration while porting code to the Lx2401A. Other issues to be considered for migration are as follows.
PLL
The PLL used in the Lx2401A is different than the one used in the 240xA family. The Lx2401A PLL does not
need the external loop-filter components. The PLL is bypassed when the TMS and TRST
pins are sensed low
at reset.
NOTE: The device may come up in PLL bypass mode if the TMS and TRST
pins are sensed low when the
emulator/debugger is brought up (with the XDS510/XDS510PP/XDS510PP+ pod connected to the target
hardware). If this happens, the device reset pin (RS
) must be activated once (after the emulator is up and
running) to bring it out of PLL bypass mode. Note that this is a concern only when the JTAG connector is
connected for debug and does not have an impact when the code is free-run without the JTAG connector—i.e.,
there are no issues when the target hardware is powered up without the JTAG connector. Before attempting
to program flash through JTAG, it must be ensured that the PLL is not in bypass mode.
on-chip bootloader
Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the
BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the
TDI, TRST
, and RS pins as described below. The on-chip bootloader is invoked when:
TRST
=0
RS =0
TDI = 0
(In addition to the three pins mentioned above, the application must ensure that PDPINTA
stays high during the
execution of the boot ROM code.) Since it has an internal pulldown, the TRST
pin will be low, provided the JTAG
connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is
low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected
(TRST
= 1), it can be achieved by writing a “0” into bit 3 of the SCSR2 register.
GPIO
The multiplexing scheme of the GPIO pins with other functional pins is different in the Lx2401A. Because of this,
the bit assignments for the MCRA, PADATDIR, and PBDATDIR registers of the Lx2401A is not compatible with
the bit assignments of the 240xA family.