Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V
CCA
and V
SSA
.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V
SS
and V
CC
from coupling into the ADC analog stage. All ADC specifications
are given with respect to V
SSA
unless otherwise noted.
Resolution 10-bit (1024 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic Assured. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode 000h to 3FFh (000h for V
I
≤ V
SSA
; 3FFh for V
I
≥ V
CCA
). . . . . . . . . . . . . . . . . . . . . . .
Conversion time (including sample time) 500 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
V
CCA
†
Analog supply voltage 3.0 3.3 3.6 V
V
SSA
†
Analog ground 0 V
V
AI
Analog input voltage, ADCIN00−ADCIN04 V
REFLO
V
REFHI
V
†
V
CCA
and V
SSA
must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.
ADC operating frequency
MIN MAX UNIT
ADC operating frequency 2 30 MHz
operating characteristics over recommended operating condition ranges
PARAMETER DESCRIPTION MIN TYP MAX UNIT
I
ADCIN
Analog input leakage 1 mA
C
ai
Analog input capacitance
Typical capacitive load on
Non-sampling 10
pF
C
ai
Analog input capacitance
Typical capacitive load on
analog input pin
Sampling 30
pF
E
DNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value
±2 LSB
E
INL
Integral nonlinearity error
Maximum deviation from the best straight line
through the ADC transfer characteristics, excluding
the quantization error
±2 LSB
t
d(PU)
Delay time, power-up to ADC
valid
Time to stabilize analog stage after power-up 10 ms
Z
AI
Analog input source impedance
Analog input source impedance needed for
conversions to remain within specifications at min
t
w(SH)
10 Ω
Zero-offset error 8 10 LSB