Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
interrupt timing
INT refers to XINT1, XINT2, and PDPINTA.
switching characteristics over recommended operating conditions (see Figure 36)
PARAMETER MIN MAX UNIT
t
d(PDP-PWM)HZ
Delay time, PDPINTA low to PWM
if bit 6 of SCSR2 = 0 (6 + 1)t
c(CO)
+ 12
†
ns
t
d(PDP-PWM)HZ
Delay time, PDPINTA low to PWM
high-impedance state
if bit 6 of SCSR2 = 1
(12+ 1)t
c(CO)
+ 12
†
ns
t
d(INT)
Delay time, INT low/high to interrupt-vector
fetch
10t
c(CO)
+ t
w(INT)
ns
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 36)
MIN MAX UNIT
t
w(INT)
Pulse duration, INT input low/high
if bit 6 of SCSR2 = 0
6t
c(CO)
ns
t
w(INT)
Pulse duration, INT input low/high
if bit 6 of SCSR2 = 1
12t
c(CO)
ns
t
w(PDP)
Pulse duration, PDPINTA input low
if bit 6 of SCSR2 = 0
6t
c(CO)
ns
t
w(PDP)
Pulse duration, PDPINTA input low
if bit 6 of SCSR2 = 1
12t
c(CO)
ns
PWM
†
PDPINTA
CLKOUT
t
w(PDP)
t
d(PDP-PWM)HZ
XINT1, XINT2
t
w(INT)
Interrupt Vector
t
d(INT)
†
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA
is taken
high depends on the state of the FCOMPOE bit.
A0−A15
(Internal Bus)
Figure 36. External Interrupts Timing