Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
LPM2 wake-up timing
switching characteristics over recommended operating conditions (see Figure 33)
PARAMETER MIN MAX UNIT
t
d(PDP-PWM)HZ
Delay time, PDPINTA low to PWM
if bit 6 of SCSR2 = 0 (6 + 1)t
c(CO)
+ 12
†
ns
t
d(PDP-PWM)HZ
Delay time, PDPINTA low to PWM
high-impedance state
if bit 6 of SCSR2 = 1
(12+ 1)t
c(CO)
+ 12
†
ns
t
d(INT)
Delay time, INT low/high to interrupt-vector
fetch
10t
c(CO)
+ t
w
(PDP−WAKE) ns
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 33)
MIN MAX UNIT
t
w(PDP−WAKE)
Pulse duration, PDPINTA input low
if bit 6 of SCSR2 = 0 6t
c(CO)
ns
t
w(PDP−WAKE)
Pulse duration, PDPINTA input low
if bit 6 of SCSR2 = 1 12t
c(CO)
ns
t
p
PLL lock-up time 98304t
c(CI)
cycles
PWM
PDPINTA
CLKOUT
‡§
t
w(PDP−WAKE)
t
d(PDP-PWM)HZ
CPU Status
Interrupt Vector
¶
or
Next Instruction
#
t
d(INT)
XTAL1
Oscillator Disabled
CLKIN
t
p
t
OSC
†
CPU IDLE State (LPM2)
†
t
OSC
is the oscillator start-up time.
‡
CLKOUT frequency after LPM2 wake-up will be the same as that upon entering LPM2 (x4 shown as an example).
§
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT
waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
¶
PDPINTA interrupt vector, if PDPINTA interrupt is enabled.
#
If PDPINTA interrupt is disabled.
Figure 33. LPM2 Wakeup Using PDPINTA