Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block diagram of the LC2401A DSP controller
XTAL1/CLKIN
XTAL2
V
SSA
V
CCA
ADCIN00−ADCIN04
SCIRXD/IOPB4
SCITXD/IOPB3
Port A(0−7) IOPA[0:7]
‡
Port B(0−5) IOPB[0:5]
†
TDO/IOPB2
TDI/OPB5
TRST
TCK/IOPB1
TMS/XF
DARAM (B0)
256 Words
DARAM (B1)
256 Words
DARAM (B2)
32 Words
C2xx
DSP
Core
PLL Clock
10-Bit ADC
(With Twin
Autosequencer)
RS
V
DD
(3.3 V)
V
SS
SARAM (512 Words)
ROM
(8K Words)
Event Manager A
D 1 × Capture Input
D 7 × Compare/PWM
Output
D 2 × GP Timers/PWM
SCI
Digital I/O
(Shared With
Other Pins)
JTAG Port
XF
PWM1/IOPA1
PWM5/IOPA5
PWM6/IOPA6
PWM3/IOPA3
PWM4/IOPA4
PWM2/IOPA2
PDPINTA
/IOPA0
XINT1
†
ADCSOC
‡
XINT2
‡
CLKOUT
‡
CAP1
‡
T2PWM
†
†
T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0.
‡
XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.
WD