Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
69
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low-power mode timing (continued)
t
d(EX)
t
d(IDLE−COH)
t
d(IDLE−OSC)
RESET
CLKOUT
A0−A15
t
d(WAKE−OSC)
t
w(RSL)
t
p
†
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
‡
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 32. HALT Mode − LPM2