Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
68
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
low-power mode timing
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 30, Figure 31, and Figure 32)
PARAMETER LOW-POWER MODES MIN TYP MAX UNIT
t
d(WAKE-A)
Delay time, CLKOUT switching to
IDLE1 LPM0 12 × t
c(CO)
ns
t
d(WAKE-A)
Delay time, CLKOUT switching to
program execution resume
IDLE2
LPM1 15 × t
c(CO)
ns
t
d(IDLE-COH)
Delay time, Idle instruction executed to
CLKOUT high
IDLE2 LPM1 4t
c(CO)
ns
t
d(WAKE-OSC)
Delay time, wake-up interrupt
asserted to oscillator running
HALT
{PLL/OSC power down}
LPM2
OSC start-up
and PLL lock
time
ms
t
d(IDLE-OSC)
Delay time, Idle instruction executed to
oscillator power off
{PLL/OSC power down}
LPM2
4t
c(CO)
ns
t
d(EX)
Delay time, reset vector executed after RS high
36H ns
WAKE INT
§
CLKOUT
†‡
A0−A15
t
d(WAKE−A)
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
§
WAKE INT can be any valid interrupt or RESET.
Figure 30. IDLE1 Entry and Exit Timing − LPM0
t
d(WAKE−A)
t
d(IDLE−COH)
WAKE INT
§
CLKOUT
†‡
A0−A15
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
§
WAKE INT can be any valid interrupt or RESET.
Figure 31. IDLE2 Entry and Exit Timing − LPM1