Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RS timing (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5t
c(CO)
]
(see Figure 29)
PARAMETER MIN MAX UNIT
t
w(RSL1)
Watchdog reset pulse width
128t
c(CI)
ns
t
d(EX)
Delay time, reset vector executed after PLL lock time
36H ns
t
p
PLL lock time (input cycles)
98304t
c(CI)
ns
XTAL1
†
CLKOUT
§
RS
t
w(RSL1)
t
p
t
d(EX)
CLKIN
TDI
‡
I/Os
TDI/OPB5
Code-Dependent
BOOT_EN
Hi-Z
†
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
‡
The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin
functions as TDI (if TRST
is high) or OPB5 (if TRST is low).
§
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 29. Watchdog Initiated Reset