Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RS timing
timing requirements for a reset [H = 0.5t
c(CO)
] (see Figure 27 and Figure 28)
MIN NOM MAX UNIT
t
w(RSL)
Pulse duration, stable CLKIN to RS high
8t
c(CI)
†
cycles
t
w(RSL2)
Pulse duration, RS low
8t
c(CI)
cycles
t
p
PLL lock-up time 98304t
c(CI)
cycles
t
d(EX)
Delay time, reset vector executed after PLL lock time
36H cycles
†
During power-on reset, the device can continue to hold the RS
pin low for another 128 CLKIN cycles.
XTAL1
(See
Note B)
RS
t
w(RSL)
t
p
t
d(EX)
V
DD
/V
DDO
CLKIN
TDI
(See
Note D)
t
OSCST
(See Note C)
I/Os
TDI/OPB5
Code-Dependent
CLKOUT
(See
Note E)
BOOT_EN
Hi-Z
NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST
of the device is not driven high before
the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New
generation emulators such as SPI515 and XDS510 USB emulators have a built-in protection mechanism to take care of this
requirement.
B. XTAL1 refers to the internal oscillator clock if an on-chip oscillator is used.
C. t
OSCST
is the oscillator start-up time, which is dependent on crystal/resonator and board design.
D. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase,
this pin functions as TDI (if TRST
is high) or OPB5 (if TRST is low).
E. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The
CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal
to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 27. Power-On Reset
XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital.
XDS510 and XDS510PP, are trademarks of Texas Instruments.