Datasheet

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 
SPRS161K − MARCH 2001 − REVISED JULY 2007
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
external reference crystal/clock with PLL circuit enabled
timing with the PLL circuit enabled
PARAMETER MIN MAX UNIT
Resonator 4 13
f
x
Input clock frequency
†
Crystal
4 20
MHz
f
x
Input clock frequency
†
CLKIN 4 20
MHz
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 26)
PARAMETER PLL MODE MIN TYP MAX UNIT
t
c(CO)
Cycle time, CLKOUT
X4 mode
†
25 ns
t
f(CO)
Fall time, CLKOUT 4 ns
t
r(CO)
Rise time, CLKOUT 4 ns
t
w(COL)
Pulse duration, CLKOUT low LF2401A X4 mode
†
@ 2 mA load H−3 H H+3 ns
t
w(COH)
Pulse duration, CLKOUT high LF2401A X4 mode
†
@ 2 mA load H−3 H H+3 ns
t
w(COL)
Pulse duration, CLKOUT low LC2401A X4 mode
†
@ 2 mA load H−5 H H+5 ns
t
w(COH)
Pulse duration, CLKOUT high LC2401A X4 mode
†
@ 2 mA load H−5 H H+5 ns
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum.
timing requirements (see Figure 26)
MIN MAX UNIT
t
c(Cl)
Cycle time, XTAL1/CLKIN
250 ns
t
f(Cl)
Fall time, XTAL1/CLKIN 5 ns
t
r(Cl)
Rise time, XTAL1/CLKIN 5 ns
t
w(CIL)
Pulse duration, XTAL1/CLKIN low as a percentage of t
c(Cl)
40 60 %
t
w(CIH)
Pulse duration, XTAL1/CLKIN high as a percentage of t
c(Cl)
40 60 %
XTAL1/CLKIN
t
c(CI)
t
w(CIL)
t
w(CIH)
t
f(Cl)
t
r(Cl)
t
c(CO)
t
w(COH)
t
w(COL)
t
r(CO)
t
f(CO)
CLKOUT
Figure 26. CLKIN-to-CLKOUT Timing With PLL and External Clock in ×4 Mode