Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
watchdog (WD) timer module (continued)
55 + AA
Detector
WDCNTR.7−0
6-Bit
Free-
Running
Counter
/64
/32
/16
/8
/4
/2
111
110
101
100
011
010
001
000
WDCLK
System
Reset
System
Reset
CLR
One-Cycle
Delay
Watchdog
Reset Key
Register
8-Bit Watchdog
Counter
CLR
Bad WDCR Key
Good Key
Bad Key
WDPS
WDCR.2−
0
210
WDKEY.7−0
WDCHK2−0
WDCR.5−3
†
WDCR.7
WDFLAG
Reset Flag
PS/257
WDDIS
WDCR.6
101
(Constant
Value)
3
3
On-Chip
Oscillator or
External
Clock
÷ 512 PLL
CLKOUT CLKIN
3-bit
Prescaler
System
Reset
Request
Internal
Pullup
RS pin
†
Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset.
Figure 19. Block Diagram of the WD Module