Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
47
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clock domains (continued)
Table 9. Low-Power Modes Summary
LOW-POWER MODE
LPMx BITS
SCSR1
[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
FLASH
POWER
EXIT
CONDITION
CPU running normally XX On On On On On On —
IDLE1 − (LPM0) 00 Off On On On On On
Peripheral
Interrupt,
External Interrupt,
Reset,
PDPINTA
IDLE2 − (LPM1) 01 Off Off On On On On
Wakeup
Interrupts,
External Interrupt,
Reset,
PDPINTA
HALT − (LPM2)
[PLL/OSC power down]
1X Off Off Off Off Off Off
†
Reset,
PDPINTA
†
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357).
other power-down options
2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these
peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
Refer to the SCSR1 register for details on the peripheral clock enable bits.