Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PLL-based clock module
The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 17 for the PLL Clock Module Block Diagram and Table 8 for clock rates.
The PLL-based clock module provides two modes of operation:
D Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
D External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
XTAL2
XTAL1/CLKIN
PLL
XTAL
OSC
CLKOUT
F
in
3-bit
PLL Select
(SCSR1.[11:9])
RESONATOR/
CRYSTAL
C
b1
C
b2
Figure 17. PLL Clock Module Block Diagram
Table 8. PLL Clock Selection Through Bits (11−9) in SCSR1 Register
CLK PS2 CLK PS1 CLK PS0 CLKOUT
0 0 0 4 × F
in
0 0 1 2 × F
in
0 1 0 1.33 × F
in
0 1 1 1 × F
in
1 0 0 0.8 × F
in
1 0 1 0.66 × F
in
1 1 0 0.57 × F
in
1 1 1 0.5 × F
in
Default multiplication factor after reset is (1,1,1), i.e., 0.5 × F
in
.
CAUTION:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN
used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot
ROM” section for more details.